With the continuous trend towards the miniaturization of semiconductor devices, many problems arise. For example, the electrical field in the channel region increases with the shortening of the length of the channel region. This increased electrical field, which has a rather high energy, makes the carriers at the junction of drain region and channel region, that is, the carriers at the highest electrical field, travel through a gate oxide layer and get trapped in a gate electrode. The trapped carriers will cause gate leakage current which can adversely influence the reliability of the device. This so-called "hot electron effect" has become a serious problem encountered in the scaling down of VLSI devices.
On the other hand, the shrinking of the channel length increases the probability of encountering coupling between the depletion region of source-substrate junction and that of drain-substrate junction in the substrate. The coupling of the depletion regions is the so-called "punchthrough effect" and severely limits the normal operation range of a MOS device. The punchthrough effect, which is one of the short channel effects, is much more significant in a lightly-doped drain (LDD) MOS device, since the junctions between its lightly-doped regions and substrate have wider depletion regions that extend into the channel region in the substrate.
A fabrication process for making lightly-doped drain and source regions for ICs has been proposed. Its process steps in its various stages are shown in the cross-sectional views in FIGS. 1A to 1C.
Referring to FIG. 1A, a gate oxide layer 12 and a gate electrode 14 are first formed in sequence on a P-type silicon substrate 10. Then, a first ion implantation to implant N-type ions is applied to form lightly-doped source/drain regions 16 at the two sides of gate electrode 14.
Referring next to FIG. 1B, sidewall spacers 18 are formed on each side wall of gate electrode 14 by, for example, depositing a layer of oxide and then etching back by plasma etching. A second ion implantation is applied to implant N-type ions, forming heavily-doped source/drain regions 19. Because sidewall spacers 18 obstruct the impurities from entering into lightly-doped regions 16 during this second implantation process, the implantation concentration in regions 16 remain relatively light as compared to that in regions 19.
The structure of FIG. 1B is then subjected to an annealing process to activate the implanted impurities. The resulting structure is shown in FIG. 1C, in which due to the activation, the edges, as indicated by numeral 15, of the lightly-doped regions 16 extend slightly inside the channel region.
A PMOS device can similarly be prepared from an N-type substrate by the above conventional process. A final structure of this PMOS device is shown in FIG. 1D.
The above proposed LDD transistor device utilizes lightly-doped regions 16 to shift the high energy electrical field region away from the channel region to reduce the possibility of the electrons traveling through the gate oxide layer. Lowering the highest electrical field in the channel region and concurrently changing the location of the peak value thereof, will diminish the "hot electron effect". However, in spite of the short channel effects such as the punchthrough effect, as the lightly-doped source/drain regions underneath spacers 18 have high sheet-resistance and therefore the conventional LDD transistor devices have lower saturation current, the electrical performance of the device in practical applications, such as driving ability and transition speed, becomes unsatisfactory. Moreover, the threshold voltage of such conventional lightly-doped drain transistor devices is also not satisfactory.
Therefore a need still exists for ways to effectively overcome both short channel and hot electron effects without degradation in device performance.